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primary cache Translation Look-aside Buffer direct mapped cache secondary cache fully associative cache ARM710 set associative cache buffered write-through cache coherency cache conflict buffer overflow backside cache cache line buffer circular buffer virtual cache Smartdrive flush cache miss cache hit Pipeline Burst Cache cache SPARCstation 10 proxy server hardware circular buffer least recently used blowing your buffer Motorola 68020 AMD 29000 sector mapping level 2 cache level 1 cache cache consistency level one cache cache block level two cache PB Cache second level cache base 64 Pipelined Burst Cache marshalling L2 cache L1 cache cache memory Group-Sweeping Scheduling Z-buffer write-back frame buffer replacement algorithm MESI protocol Intel i960 pipeline thrash i860 MIPS Technologies, Inc. ARM7 hit Z shell Scalable Coherent Interface Cache On A STick more...